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| DATA SHEET MOS INTEGRATED CIRCUIT PD178076,178078,178096,178098 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD178076, 178078, 178096, and 178098 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning systems. These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for system control. As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In addition, the PD178076 and 178078 have an asynchronous serial interface (UART) mode, and the PD178096 and 178098 have an IEBusTM controller. Moreover, a flash memory model, the PD178F098, that operates in the same supply voltage range as the mask ROM models, and various development tools are also under development. For the detailed functional description, refer to the following User's Manuals: PD178078, 178098 Subseries User's Manual : U12790E 78K/0 Series User's Manual - Instruction : U12326E FEATURES * High-capacity ROM and RAM Item Program Memory (ROM) Part Number Data Memory Internal high-speed RAM Internal buffer RAM 48K bytes 60K bytes 1024 bytes 32 bytes Internal extension RAM 1024 bytes 2048 bytes PD178076, 178096 * Instruction cycle: PD178078, 178098 0.32 s (with crystal resonator of fX = 6.3 MHz) * Hardware for PLL frequency synthesizer phase comparator, charge pump dual modulus prescaler, programmable divider, * Many internal hardware units General-purpose I/O ports, A/D converter, serial interface (UART mode: PD178076 and 178078 * Vectored interrupt sources * Supply voltage * PD178076, 178078: 22 * PD178096, 178098: 21 only), IEBus controller (PD178096 and 178098 only), timers, frequency counter, power-ON clear circuit :VDD = 4.5 to 5.5 V (during PLL and CPU operations) :VDD = 3.5 to 5.5 V (during CPU operation) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12885EJ3V0DS00 Date Published June 2000 N CP(K) Printed in Japan The mark shows major revised points. (c) 1997, 2000 PD178076, 178078, 178096, 178098 APPLICATION FIELD Car stereos ORDERING INFORMATION Part Number Package 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) PD178076GF-xxx-3BA PD178078GF-xxx-3BA PD178096GF-xxx-3BA PD178098GF-xxx-3BA Remark xxx indicates ROM code suffix, which is Exx when the I2C bus is used. 2 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 DEVELOPMENT OF 8-BIT DTS SERIES Models under mass production Models under development Flash memory model or PROM model Mask ROM model 80 pins PD178F048 Internal OSD controller 8-bit PWM x 4 channels 14-bit PWM x 1 channel 80 pins PD178048 subseries Internal OSD controller 8-bit PWM x 4 channels 14-bit PWM x 1 channel 100 pins PD178098 subseries Internal IEBus controller 100 pins PD178F098 Internal IEBus controller and UART 100 pins PD178078 subseries Internal UART 80 pins PD178F134 Internal LCD and UART 80 pins PD178034 subseries Internal LCD and UART 80 pins PD178F124 Internal UART 80 pins PD178024 subseries Internal UART 80 pins PD178018A subseries 80 pins PD178P018A 80 pins PD178003 subseries Limits functions of PD178018A subseries Data Sheet U12885EJ3V0DS00 3 PD178076, 178078, 178096, 178098 FUNCTIONAL OUTLINE (1/2) Item Internal memory ROM PD178076 48K bytes PD178078 60K bytes PD178096 48K bytes PD178098 60K bytes High-speed RAM 1024 bytes Buffer RAM Extension RAM 32 bytes 1024 bytes 2048 bytes 1024 bytes 2048 bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) * 0.32 s/0.64 s/1.27 s/2.54 s/5.08 s (with crystal resonator of fX = 6.3 MHz) * 0.44 s/0.89 s/1.78 s/3.56 s/7.11 s (with crystal resonator of fX = 4.5 MHz)Note 1 * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test Boolean operation) BCD adjustment, etc. : 80 pins : 8 pins : 64 pins 8 pins * 3-wire/SBI/2-wire/I2C bus Note 2 mode selectable: 1 channel * 3-wire mode: 1 channel * 3-wire mode (with automatic transmit/ receive function of up to 32 bytes): 1 channel Provided : : : : 1 1 2 1 channel channel channels channel General-purpose register Minimum instruction execution time Instruction set I/O port Total * CMOS input * CMOS I/O * N-ch open-drain output : A/D converter Serial interface 8-bit resolution x 8 channels * 3-wire/SBI/2-wire/I2C bus Note 2 mode selectable: 1 channel * 3-wire mode: 1 channel * 3-wire mode (with automatic transmit/ receive function of up to 32 bytes): 1 channel * UART mode: 1 channel Not provided * * * * Basic timer (timer carry FF (10 Hz)) 16-bit timer/event counter 8-bit timer/event counter Watchdog timer IEBus controller Timer Buzzer output BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of fX = 6.3 MHz) Notes 1. When using the IEBus controller of the PD178096 or 178098, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz crystal resonator. 2. When the I2C bus mode is used (including when the mode is implemented in software without using the peripheral hardware), consult NEC when ordering a mask. 4 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 (2/2) Item Vectored interrupt source Non-maskable Software PLL frequency synthesizer Reference frequency Charge pump Phase comparator Frequency counter Frequency measurement * AMIFC pin: For 450-kHz counting * FMIFC pin: For 450-kHz/10.7-MHz counting * HALT mode * STOP mode * Reset by RESET pin * Internal reset by watchdog timer * Reset by power-ON clear circuit * Detection of less than 4.5 VNote (Reset does not occur, however.) * Detection of less than 3.5 VNote (during CPU operation) * Detection of less than 2.3 VNote (in STOP mode) * VDD = 4.5 to 5.5 V (during CPU, PLL operation) * VDD = 3.5 to 5.5 V (during CPU operation) * 100-pin plastic QFP (14 x 20) Division mode Maskable PD178076 Internal : 13 External: 8 Internal: 1 1 2 types PD178078 PD178096 Internal : 12 External: 8 PD178098 * Direct division mode (VCOL pin) * Pulse swallow mode (VCOL and VCOH pins) Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz) Error out output: 2 pins Unlock detectable in software Standby function Reset Supply voltage Package Note These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these. Data Sheet U12885EJ3V0DS00 5 PD178076, 178078, 178096, 178098 PIN CONFIGURATION (Top View) * 100-pin plastic QFP (14 x 20) PD178076GF-xxx-3BA, 178078GF-xxx-3BA PD178096GF-xxx-3BA, 178098GF-xxx-3BA GNDPORT VDDPORT P47 P46 P45 P44 P43 P42 P41 P40 P67 P66 P65 P64 P63 P62 P61 P60 GND1 P07/INTP7 P00/INTP0 P01/INTP1 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P70/SI3 P71/SO3 P72/SCK3 P73 P50 P51 P52 P53 P54 P55 P56 P57 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 AVDD P14/ANI4 P15/ANI5 P16/ANI6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P06/INTP6 P05/INTP5 P04/INTP4 P124 P123 P122 P121 /RX0 P120 /TX0 P77 P76 P75[/TXD0] P74[/RXD0] P137 P136 P135 P134 P133 P132 P131/TO51 P130/TO50 P37/BUZ P36/BEEP0 P35/TI51 P34/TI50 P33/TI01 P32/TI00 P31/TO0 P30/VM45 P03/INTP3 P02/INTP2 6 P17/ANI7 AVSS REGCPU VDD REGOSC X2 X1 GND0 P100 GND2 P101/AMIFC P102/FMIFC VDDPLL VCOH VCOL GNDPLL EO0 EO1 IC RESET Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Cautions 1. Directly connect the IC (Internally Connect) pin to GND0, GND1, or GND2. 2. Keep the voltage at AVDD, VDDPORT, and VDDPLL pins same as that at the VDD pin. 3. Keep the voltage at AVSS, GNDPORT, and GNDPLL pins same as that at GND0, GND1, or GND2. 4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-F capacitor. Remark [ ] : PD178076 and 178078 only { }: PD178096 and 178098 only Pin Name AMIFC ANI0-ANI7 AVDD AVSS BUSY BEEP0, BUZ EO0, EO1 FMIFC GNDPLL GND0-GND2 IC INTP0-INTP7 P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P100-P102 P120-P124 : AM intermediate frequency counter input : A/D converter input : A/D converter power supply : A/D converter ground : Busy output : Buzzer output : Error out output : FM intermediate frequency counter input : PLL ground : Ground : Internally connected : Interrupt input : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 10 : Port 12 P130-P137 REGCPU REGOSC RESET RXD0Note 1 RX0Note 2 SB0, SB1 SCL SDA0, SDA1 SI0, SI1, SI3 SO0, SO1, SO3 STB TI00, TI01 TI50, TI51 TO0 TO50, TO51 TXD0Note 1 TX0Note 2 VCOL, VCOH VDDPORT VDDPLL VDD VM45 X1, X2 : Port 13 : Regulator for CPU power supply : Regulator for oscillation circuit : Reset input : UART0 serial data input : IEBus serial data input : Serial data bus input/output : Serial clock input/output : Serial data input/output : Serial data input : Serial data output : Strobe output : 16-bit timer capture trigger input : 8-bit timer clock input : 16-bit timer output : 8-bit timer output : UART0 serial data output : IEBus serial data output : Local oscillation input : Port power supply : PLL power supply : Power supply : VDD = 4.5 V monitor output : Crystal resonator SCK0, SCK1, SCK3 : Serial clock input/output Notes 1. PD178076 and 178078 only 2. PD178096 and 178098 only Data Sheet U12885EJ3V0DS00 7 PD178076, 178078, 178096, 178098 BLOCK DIAGRAM (1) PD178076, 178078 TO0/P31 TI00/P32 TI01/P33 TI50/P34 TO50/P130 TI51/P35 TO51/P131 16-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER 50 8-bit TIMER/ EVENT COUNTER 51 WATCHDOG TIMER PORT 0 8 P00-P07 PORT 1 8 P10-P17 PORT 2 8 P20-P27 PORT 3 8 P30-P37 BASIC TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI3/P70 SO3/P71 SCK3/P72 TXD0/P75 RXD0/P74 INTP0/P00INTP7/P07 BEEP0/P36 BUZ/P37 RESET X1 X2 VDDPORT GNDPORT VDD 78K/0 CPU CORE ROM PD178078 : 60 Kbyte PD178076 : 48 Kbyte PORT 4 8 P40-P47 SERIAL INTERFACE 0 PORT 5 8 P50-P57 PORT 6 8 P60-P67 SERIAL INTERFACE 1 PORT 7 8 P70-P77 SERIAL INTERFACE 3 UART0 RAM PD178078 : 3 Kbyte PD178076 : 2 Kbyte PORT10 3 P100-P102 PORT 12 5 P120-P124 PORT 13 8 INTERRUPT CONTROL 8 P130-P137 ANI0/P10ANI7/P17 AVDD AVSS AMIFC/P101 FMIFC/P102 EO0 EO1 VCOL VCOH VDDPLL GNDPLL IC GND2 8 BUZZER OUTPUT RESET CPU PERIPHERAL A/D CONVERTER SYSTEM CONTROL FREQUENCY COUNTER VM45/P30 REGOSC REGCPU GND0 GND1 VOLTAGE REGULATOR VOSC VCPU PLL PLL VOLTAGE REGULATOR 8 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 (2) PD178096, 178098 TO0/P31 TI00/P32 TI01/P33 TI50/P34 TO50/P130 TI51/P35 TO51/P131 16-bit TIMER/ EVENT COUNTER 8-bit TIMER/ EVENT COUNTER 50 8-bit TIMER/ EVENT COUNTER 51 WATCHDOG TIMER PORT 0 8 P00-P07 PORT 1 8 P10-P17 PORT 2 8 P20-P27 PORT 3 8 P30-P37 BASIC TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI3/P70 SO3/P71 SCK3/P72 RX0/P121 TX0/P120 INTP0/P00INTP7/P07 BEEP0/P36 BUZ/P37 RESET X1 X2 VDDPORT GNDPORT VDD 78K/0 CPU CORE ROM PD178098 : 60 Kbyte PD178096 : 48 Kbyte PORT 4 8 P40-P47 SERIAL INTERFACE 0 PORT 5 8 P50-P57 PORT 6 SERIAL INTERFACE 1 8 P60-P67 PORT 7 8 P70-P77 SERIAL INTERFACE 3 IEBus0 RAM PD178098 : 3 Kbyte PD178096 : 2 Kbyte PORT10 3 P100-P102 PORT 12 5 P120-P124 PORT 13 8 INTERRUPT CONTROL 8 P130-P137 ANI0/P10ANI7/P17 AVDD AVSS AMIFC/P101 FMIFC/P102 EO0 EO1 VCOL VCOH VDDPLL GNDPLL IC GND2 8 BUZZER OUTPUT RESET CPU PERIPHERAL A/D CONVERTER SYSTEM CONTROL FREQUENCY COUNTER VM45/P30 REGOSC REGCPU GND0 GND1 VOLTAGE REGULATOR VOSC VCPU PLL PLL VOLTAGE REGULATOR Data Sheet U12885EJ3V0DS00 9 PD178076, 178078, 178096, 178098 CONTENTS 1. PIN 1.1 1.2 1.3 FUNCTION LIST ...................................................................................................................... Port Pins .................................................................................................................................. Pins Other Than Port Pins ...................................................................................................... I/O Circuits of Pins and Recommended Connections of Unused Pins .............................. 11 11 12 14 2. MEMORY SPACE ............................................................................................................................ 18 2.1 Memory Size Select Register (IMS) ....................................................................................... 19 2.2 Internal Extension RAM Size Select Register (IXS) ............................................................. 20 FEATURES OF PERIPHERAL HARDWARE FUNCTIONS ......................................................... 3.1 Ports ......................................................................................................................................... 3.2 Clock Generation Circuit ........................................................................................................ 3.3 Timers ...................................................................................................................................... 3.4 Buzzer Output Control Circuit ............................................................................................... 3.5 A/D Converter .......................................................................................................................... 3.6 Serial Interface ........................................................................................................................ 3.7 IEBus Controller (PD178096 and 178098 only) .................................................................. 3.8 PLL Frequency Synthesizer ................................................................................................... 3.9 Frequency Counter ................................................................................................................. 21 21 22 22 26 27 28 32 35 36 3. 4. 5. 6. 7. 8. 9. INTERRUPT FUNCTION ................................................................................................................. 37 STANDBY FUNCTION .................................................................................................................... 43 RESET FUNCTION.......................................................................................................................... 43 INSTRUCTION SET ......................................................................................................................... 44 ELECTRICAL SPECIFICATIONS ................................................................................................... 47 PACKAGE DRAWING ..................................................................................................................... 63 10. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 64 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 65 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 67 10 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 1. PIN FUNCTION LIST 1.1 Port Pins (1/2) Pin Name P00-P07 I/O I/O Port 0. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P10-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40-47 I/O Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P50-P57 I/O Port 5. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P60-P67 I/O Port 6. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P70 P71 P72 P73 P74 P75 P76, P77 I/O Port 7. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input SI3 SO3 SCK3 - RXD0Note 1 TXD0Note 1 - Input - Input - Input I/O Port 3. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input Input I/O Port 1. 8-bit input port. Port 2. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input Input ANI0-ANI7 SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL VM45 TO0 TI00 TI01 TI50 TI51 BEEP0 BUZ - Function At Reset Input Shared by: INTP0-INTP7 Data Sheet U12885EJ3V0DS00 11 PD178076, 178078, 178096, 178098 1.1 Port Pins (2/2) Pin Name P100 P101 P102 P120 P121 P122-P124 P130 P131 P132-P137 Output I/O I/O I/O Port 10. 3-bit I/O port. Can be set in input or output mode in 1-bit units. Port 12. 5-bit I/O port. Can be set in input or output mode in 1-bit units. Port 13. 8-bit output port. N-ch open-drain output port (15 V withstand) Low-level output TO50 TO51 - Input Function At Reset Input AMIFC FMIFC TX0Note 2 RX0Note 2 - Shared by: - Notes 1. PD178076 and 178078 only. 2. PD178096 and 178098 only. 1.2 Pins Other Than Port Pins (1/2) Pin Name INTP0-INTP7 I/O Input Function External maskable interrupt input whose valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. SI0 SI1 SI3 SO0 SO1 SO3 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCK3 SCL STB Output N-ch open drain I/O Strobe output for serial interface automatic transmission/ reception. BUSY Input Busy input for serial interface automatic transmission/ reception. VW45 TI00 TI01 TI50 TI51 Input External count clock input to 8-bit timer 50. External count clock input to 8-bit timer 51. Input Output Input VDD = 4.5 V monitor output External count clock input to 16-bit timer 0. Input Input P30 P32 P33 P34 P35 Input P24 Input I/O Serial clock input/output to/from serial interface. Input I/O Serial data input/output to/from serial interface. N-ch open drain I/O Input Output Serial data output from serial interface. Input Input Serial data input to serial interface. Input P25/SB0/SDA0 P20 P70 P26/SB1/SDA1 P21 P71 P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P22 P72 P27/SCK0 P23 At Reset Input Shared by: P00-P07 12 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 1.2 Pins Other Than Port Pins (2/2) Pin Name TO0 TO50 TO51 BEEP0 BUZ ANI0-ANI7 EO0, EO1 Input Output Analog input to A/D converter. Error out output from charge pump of PLL frequency synthesizer. VCOL Input Inputs local oscillation frequency of PLL (in HF and MF modes). VCOH AMIFC FMIFC Input Input Input Inputs local oscillation frequency of PLL (in VHF mode). Input to AM intermediate frequency counter. Input to FM intermediate frequency or AM intermediate frequency counter. RXD0 Input Serial data input to asynchronous serial interface (UART0). Input P74 - Input Input P101 P102 - - - Input - Output I/O Output 16-bit timer 0 output. 8-bit timer 50 output. 8-bit timer 51 output. Buzzer output. Function At Reset Input Low-level output Input Shared by: P31 P130 P131 P36 P37 P10-P17 - PD178076 and 178078 only. TXD0 Output Serial data output from asynchronous serial interface (UART0). PD178076 and 178078 only. TX0 RX0 RESET X1 X2 REGOSC Output Input Input Input - - Regulator for oscillation circuit. Connect this pin to GND via 0.1-F capacitor. REGCPU - Regulator for CPU power supply. Connect this pin to GND via 0.1-F capacitor. VDD GND0-GND2 VDDPORT GNDPORT AVDD - - - - - Positive power supply. Ground. Port power supply. Port ground. A/D converter positive power supply. Keep voltage at this pin same as that at VDD. AVSS VDDPLL Note GNDPLLNote IC - A/D converter ground. Keep voltage at this pin same as that at GND0 through GND2. - - - PLL positive power supply. PLL ground. Internally connected. Directly connect this pin to GND0, GND1, or GND2. - - - - - - - - - - - - - - - - - - - - IEBus controller data output. PD178096 and 178098 only. IEBus controller data input. PD178096 and 178098 only. System reset input. Connection of crystal resonator for system clock oscillation. Input Input - - - - P120 P121 - - - - Input P75 Note Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins. Data Sheet U12885EJ3V0DS00 13 PD178076, 178078, 178096, 178098 1.3 I/O Circuits of Pins and Recommended Connections of Unused Pins Table 1-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins when they are not used. For the configuration of the I/O circuit of each pin, refer to Figure 1-1. Table 1-1. I/O Circuit Type of Each Pin (1/2) Pin Name P00/INTP0-P07/INTP7 I/O Circuit Type 8 I/O I/O Recommended Connection of Unused Pin Input: Individually connect them to VDD, VDDPORT, GND0 to GND2, or GNDPORT via resistor. Output: Leave open. Connect them to VDD, VDDPORT, GND0 to GND2, or GNDPORT. Input: Individually connect them to VDD, VDDPORT, GND0 to GND2, or GNDPORT via resistor. Output: Leave open. P10/ANI0-P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/VM45 P31/TO0 P32/TI00 P33/TI01 P34/TI50 P35/TI51 P36/BEEP0 P37/BUZ P40-P47 P50-P57 P60-P67 P70/SI3 P71/SO3 P72/SCK3 P73 P74/RXD0 P75/TXD0 P76, P77 P100 P101/AMIFC P102/FMIFC P120/TX0 P121/RX0 P122-P124 25 5-K 5 5-K 5 5-K 10-D Input I/O 5 5-K 5 5-K 5 5-K 5 5-K 5 5-K 5 14 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Table 1-1. I/O Circuit Type of Each Pin (2/2) Pin Name P130/TO50 P131/TO51 P132-P137 EO0 EO1 VCOL, VCOH REGOSC, REGCPU RESET AVDD AVSS IC 2 - DTS-AMP2 - Input - Input - Disable PLL in software and select pull-down. Connect these pins to GND0, GND1, or GND2 via 0.1-F capacitor. - Connect this pin to VDD or VDDPORT. Directly connect these pins to GND0 to GND2, or GNDPORT. DTS-EO1 I/O Circuit Type 19 I/O Output Recommended Connection of Unused Pin Open these pins. Data Sheet U12885EJ3V0DS00 15 PD178076, 178078, 178096, 178098 Figure 1-1. I/O Circuits of Respective Pins (1/2) Type 2 Type 5 VDD data P-ch IN/OUT IN output disable input enable N-ch Schmitt trigger input with hysteresis characteristics Type 5-K VDD data Type 8 VDD P-ch IN/OUT IN/OUT data P-ch output disable N-ch output disable N-ch input enable Type 10-D VDD data P-ch IN/OUT open drain output disable N-ch Type 19 OUT N-ch input enable Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as VDDPORT and GNDPORT. 16 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Figure 1-1. I/O Circuits of Respective Pins (2/2) Type 25 Type DTS-EO1 VDDPLL P-ch Comparator + - DW IN P-ch OUT N-ch VREF (Threshold voltage) input enable UP N-ch GNDPLL Type DTS-AMP VDDPLL IN Note GNDPLL Note This switch is selectable in software only for the VCOL and VCOH pins. Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as VDDPORT and GNDPORT. Data Sheet U12885EJ3V0DS00 17 PD178076, 178078, 178096, 178098 2. MEMORY SPACE Figure 2-1 shows the memory map of the PD178076, 178078, 178096, and 178098. Figure 2-1. Memory Map FFFFH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FB00H FAFFH Cannot be used Data memory space FAC0H FABFH F800H F7FFH mmmmH mmmmH-1 nnnnH+1 nnnnH Program memory space 0000H 0000H Internal ROMNotes 1, 3 0040H 003FH Vector table area FAE0H FADFH nnnnH Program area 1000H 0FFFH Cannot be used CALLF entry area Internal extension RAMNotes 1,3 0800H 07FFH Program area Cannot be usedNote 2 0080H 007FH CALLT table area Internal buffer RAM 32 x 8 bits Notes 1. The internal ROM and internal extension RAM capacities differ depending on the model (refer to the table below). Internal ROM End Address nnnnH BFFFH EFFFH Internal Extension RAM First Address mmmmH F400H F000H Target Model Name PD178076, 178096 PD178078, 178098 2. The PD178078 and 178098 do not have this unusable area. 18 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Note 3. The initial values of the memory size select register (IMS) and internal extension RAM size select register (IXS) are CFH and 0CH, respectively. The following values must be set to the registers of each model. Part Number IMS CCH CFH 0AH 08H IXS PD178076, 178096 PD178078, 178098 2.1 Memory Size Select Register (IMS) This register is used to select the capacity of the internal memory. Set CCH to this register of the PD178076 and 178096. Set CFH to the IMS of the PD178078 and 178098. Use an 8-bit memory manipulation instruction to set the IMS. This register is set to CFH at reset. Figure 2-2. Format of Memory Size Select Register (IMS) Symbol 7 6 5 4 0 3 2 1 0 Address FFF0H At reset CFH R/W R/W IMS RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 RAM2 1 Others RAM1 RAM0 1 0 1024 bytes Setting prohibited Selects internal high-speed RAM capacity RAM3 RAM2 1 1 Others 1 1 RAM1 0 1 RAM0 0 1 48K bytes 60K bytes Setting prohibited Selects internal ROM capacity Data Sheet U12885EJ3V0DS00 19 PD178076, 178078, 178096, 178098 2.2 Internal Extension RAM Size Select Register (IXS) This register is used to select the capacity of the internal extension RAM. Set 0AH of this register of the PD178076 and 178096. Set 08H of the IXS of the PD178078 and 178098. Use an 8-bit memory manipulation instruction to set the IXS. This register is set to 0CH at reset. Figure 2-3. Format of Internal Extension RAM Size Select Register (IXS) Symbol IXS 7 0 6 0 5 0 4 3 2 1 0 Address FFF4H At reset 0CH R/W R/W IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 0 Others 1 1 0 0 0 1 0 0 2048 bytes 1024 bytes Selects internal extension RAM capacity Setting prohibited 20 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS 3.1 Ports The following three types of ports are available: * CMOS input (port 1) * CMOS I/O (ports 0, 2 through 7, 10, and 12) * N-ch open-drain output (port 13) Total : 8 pins : 64 pins : 8 pins : 80 pins Table 3-1. Port Functions Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 10 Port 12 Port 13 Pin Name P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P100-P102 P120-P124 P130-P137 Function I/O port. Can be set in input or output mode in 1-bit units. Input-only port. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. N-ch open-drain output port. Data Sheet U12885EJ3V0DS00 21 PD178076, 178078, 178096, 178098 3.2 Clock Generation Circuit The instruction execution time can be changed as follows: * 0.32 s/0.64 s/1.27 s/2.54 s/5.08 s (system clock: 6.3-MHz crystal resonator) * 0.44 s/0.89 s/1.78 s/3.56 s/7.11 s (system clock: 4.5-MHz crystal resonator)Note Note When using the IEBus controller of the PD178096 and 178098, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz crystal resonator. Figure 3-1. Block Diagram of Clock Generation Circuit Prescaler Clock to other than peripheral hardware fX fX 2 X1 X2 System clock oscillator Prescaler Selector fX 22 fX 23 fX 24 Standby control circuit Wait control circuit CPU clock (fCPU) 3 STOP 0 0 0 0 0 PCC2 PCC1 PCC0 Processor clock control register (PCC) Internal bus 3.3 Timers Five timer channels are provided. * Basic timer : 1 channel * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watchdog timer : 1 channel Figure 3-2. Block Diagram of Basic Timer 6.3 MHz or 4.5 MHzNote Divider circuit INTBTM0 Note When using the IEBus controller of the PD178096 and 178098, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz crystal resonator. 22 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Figure 3-3. Block Diagram of 16-Bit Timer/Event Counter Internal bus Capture/compare control register 0 (CPU) CRC02 CRC01 CRC00 Selector INTTM00 TI01/P33 Noise rejection circuit Selector 16-bit capture/compare register 00 (CR00) Coincidence Selector fX/2 fX/22 fX/26 16-bit timer counter 0 (TM0) Coincidence Clear Output control circuit Output latch (P31) TO0/P31 fX/23 Noise rejection circuit 2 Noise rejection circuit 16-bit capture/compare register 01 (CR01) Selector PM31 TI00/P32 INTTM01 CRC02 PRM01PRM00 Prescaler mode register 0 (PRM0) TMC03 TMC02 TMC01 OVF0 16-bit timer mode control register 0 (TMC0) Internal bus OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 Timer output control register 0 (TOC0) Data Sheet U12885EJ3V0DS00 23 PD178076, 178078, 178096, 178098 Figure 3-4. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Mask circuit 8-bit compare register 50 (CR50) TI50/P34 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Coincidence Selector INTTM50 Selector 8-bit timer counter OVF 50 (TM50) Clear Selector S Q INV R TO50/P130 Output latch (P130) 3 Selector S R Level inversion TCL502 TCL501 TCL500 Timer clock select register 50 (TCL50) TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Timer mode control register 50 (TMC50) Internal bus Figure 3-5. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Mask circuit 8-bit compare register 51 (CR51) TI51/P35 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Coincidence Selector INTTM51 Selector 8-bit timer counter OVF 51 (TM51) Clear Selector S Q INV R TO51/P131 Output latch (P131) 3 Selector S R Level inversion TCL512 TCL511 TCL510 Timer clock select register 51 (TCL51) TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer mode control register 51 (TMC51) Internal bus 24 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Figure 3-6. Block Diagram of Watchdog Timer fX/28 Clock input control circuit Divider circuit Divided clock select circuit INTWDT Output control circuit RESET RUN Division mode select circuit 3 WDT mode signal OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS) WDCS2 WDCS1 WDCS0 RUN WDTM4 WDTM3 Watchdog timer clock select register (WDCS) Internal bus Watchdog timer mode register (WDTM) Data Sheet U12885EJ3V0DS00 25 PD178076, 178078, 178096, 178098 3.4 Buzzer Output Control Circuit Two types of buzzer output control circuits are provided. * BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz * BUZ ... 0.77 kHz/1.54 kHz/3.08 kHz/6.15 kHz (system clock: 6.3-MHz crystal resonator) Figure 3-7. Block Diagram of Buzzer Output Control Circuit (BEEP0) 1 kHz 1.5 kHz 3 kHz 4 kHz Output latch (P36) Selector BEEP0/P36 PM36 BEEP BEEP BEEP BEEP0 clock select CL02 CL01 CL00 register (BEEPCL0) Internal bus Figure 3-8. Block Diagram of Buzzer Output Control Circuit (BUZ) fX/210 fX/211 fX/212 fX/213 Output latch (P37) Selector BUZ/P37 PM37 BZOE BCS1 BCS0 Clock output select register (CKS) Internal bus Remark fX: System clock frequency 26 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 3.5 A/D Converter An A/D converter with a resolution of 8 bits x 8 channels is provided. Figure 3-9. Block Diagram of A/D Converter ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Sample & hold circuit Selector Voltage comparator Tap selector AVDD ADCS3 AVSS Successive approximation register (SAR) AVSS Control circuit Control Voltage circuit comparator Power-fail compare threshold value register 3 (PFT3) INTAD 4 A/D conversion result register 3 (ADCR3) ADS33 ADS32 ADS31 ADS30 ADCS3 0 FR32 FR31 FR30 0 0 0 PFEN3 PFCM3 PFHRM3 Analog input channel specification register 3 (ADS3) A/D converter mode register 3 (ADM3) Power-fail compare mode register 3 (PFM3) Internal bus Data Sheet U12885EJ3V0DS00 27 PD178076, 178078, 178096, 178098 3.6 Serial Interface The PD178076 and 178078 have four serial interface channels, and the PD178096 and 178098 have three channels. * Serial interface 0 * Serial interface 1 * Serial interface 3 * Serial interface UART0: PD178076 and 178078 only Table 3-2. Types and Functions of Serial Interfaces Function 3-wire serial I/O mode Serial interface 0 (MSB/LSB first selectable) - Serial interface 1 (MSB/LSB first selectable) (MSB/LSB first selectable) - - - - Serial interface 3 (MSB first) UART0Note - 3-wire serial I/O mode with automatic transmit/receive function SBI (serial bus interface) mode 2-wire serial I/O mode I2C bus mode UART (asynchronous serial interface) mode - - (MSB first) (MSB first) (MSB first) - - - - - - - - (Dedicated baud rate generator) Note PD178076 and 178078 only. 28 Data Sheet U12885EJ3V0DS00 Figure 3-10. Block Diagram of Serial Interface 0 Internal bus Serial operating mode register 0 (CSIM0) CSIE0 COI WUP CSIM CSIM CSIM CSIM 04 03 02 01 0 Slave address register 0 (SVA0) Coincidence BSYE Control circuit SI0/SB0/SDA0/P25 PM25 Output control Serial bus interface control register 0 (SBIC0) BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SVAM Selector P25 output latch Selector PM26 Output control Serial I/O shift register (SIO0) CLR SET D Q SO0/SB1/SDA1/P26 Note P26 output latch Note Acknowledge output circuit Stop condition/ start condition/ acknowledge detector Serial clock counter ACKD CMDD RELD Data Sheet U12885EJ3V0DS00 WUP Interrupt request signal generator INTCSI0 CLD SCK0/SCL/P27 PM27 Output control PD178076, 178078, 178096, 178098 Serial clock control circuit Selector 1/16 divider Selector fX/22-fX/29 CSIM01 P27 output latch CSIM01 2 4 CLD SIC SVAM CLC WREL WAT1 WAT0 SCL03 SCL02 SCL01 SCL00 Serial interface clock select register 0 (SCL0) Interrupt timing specification register 0 (SINT0) Internal bus Note Example in I2C bus mode operation. Remark Output Control performs selection between CMOS output and N-ch open drain output. 29 Selector Selector 30 Internal bus Internal buffer RAM ATE DIR1 Serial I/O shift register 1 (SIO1) DIR1 SI1/P20 Figure 3-11. Block Diagram of Serial Interface 1 Automatic data transmit/ receive address pointer register (ADTP) Internal bus Automatic data transmit/receive interval specification register (ADTI) ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Coincidence ADTI0-ADTI4 Automatic data transmit/receive control register (ADTC) CSIE1 DIR1 TRF Selector P21 output latch 5-Bit counter Serial operating mode register 1 (CSIM1) ATE LSCK1 SCL11 SCL10 RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0 Data Sheet U12885EJ3V0DS00 PM21 SO1/P21 PM23 STB/P23 BUSY/P24 Handshake PD178076, 178078, 178096, 178098 ARLD Serial clock counter SIO1 write Clear CSIE1 R Q S LSCK1 Selector fX/24-fX/26 INTCSI1 SCK1/P22 PM22 P22 output latch PD178076, 178078, 178096, 178098 Figure 3-12. Block Diagram of Serial Interface 3 Internal bus 8 SI3/P70 PM71 SO3/P71 SCK3/P72 P71 output latch Serial clock counter Serial clock control circuit PM72 P72 output latch Interrupt request signal generation circuit INTCSI3 fX/24 fX/25 fX/26 Serial I/O shift register 3 (SIO3) Selector Figure 3-13. Block Diagram of Serial Interface UART0 (PD178076 and 178078 only) Internal bus Asychronous serial interface mode register 0 (ASIM0) Receive buffer register 0 (RXB0) Asynchronous serial interface status register 0 (ASIS0) RXD0/P74 Receive shift register 0 (RX0) PE0 FE0 OVE0 Transmit shift register (TXS0) TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 0 TXD0/P75 Reception control circuit PM75 (parity check) P75 output latch INTSER0 INTSR0 Transmission control circuit (parity append) INTST0 Baud rate generator fX/2-fX/28 TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00 Baud rate generator control register 0 (BRGC0) Internal bus Data Sheet U12885EJ3V0DS00 31 PD178076, 178078, 178096, 178098 3.7 IEBus Controller (PD178096 and 178098 only) The PD178096 and 178098 have an IEBus controller. The functions of this IEBus controller are limited as compared with the existing IEBus interface functions of the PD78098 subseries. Table 3-3 compares the interfaces of the PD78098 subseries and PD178098 subseries. Table 3-3. Comparison of IEBus Interface (between PD78098 Subseries and PD178098 Subseries) Item Communication mode Internal system clock Internal buffer size PD78098 Subseries IEBus Modes 0, 1, and 2 fX = 6.0 (6.29) MHz Transmit buffer: 33 bytes (FIFO) Receive buffer: 40 bytes (FIFO) Up to 4 frames can be received. Communication start processing (data setting) Setting and management of each communication status Writing data to transmit buffer Reading data from receive buffer PD178098 Subseries IEBus Fixed to mode 1 fX = 6.3 MHzNote Transmit buffer: 1 byte Receive buffer: 1 byte Communication start processing (data setting) Setting and management of each communication status Writing data per 1 byte Reading data per 1 byte Management of transmission such as slave status Management of multiple frames, re-master request processing Bit processing (modulation/demodulation, error detection) Field processing (generation/management) Arbitration result detection Parity processing (generation/error detection) Automatic answering of ACK/NACK Automatic data re-transmission processing CPU processing Hardware processing Bit processing (modulation/demodulation, error detection) Field processing (generation/management) Arbitration result detection Parity processing (generation/error detection) Automatic answering of ACK/NACK Automatic data re-transmission processing Automatic re-master processing Transmission processing such as automatic slave status Multiple frame reception processing Note The IEBus controller of the PD178098 subseries operates at fX = 6.3 MHz, and not at fX = 4.5 MHz. Remark fX: System clock frequency 32 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Figure 3-14. Block Diagram of IEBus Controller (PD178096 and 178098 only) CPU interface block 8 Internal registers BCR0 (8) 8 12 12 12 8 8 8 12 UAR (12) 12 SAR (12) 12 PAR (12) 8 CDR (8) 8 DLR (8) 8 8 8 8 8 8 DR (8) USR (8) 8 ISR (8) SSR (8) SCR (8) CCR (8) 8 8 8 8 Internal bus 8 8 RX0/P121 NF MPX TX/RX PSR (8 bits) 12-bit latch Comparator Collision detection Interrupt control circuit Interrupt control block INT request 12 TX0/P120 MPX Parity generation error detection ACK generation IEBus interface block CLK 5 Internal bus R/W Bit processing block Field processing block Data Sheet U12885EJ3V0DS00 33 PD178076, 178078, 178096, 178098 The IEBus mainly consists of the following six internal blocks: * CPU interface block * Interrupt control block * Internal registers * Bit processing block * Field processing block * IEBus interface block 34 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 3.8 PLL Frequency Synthesizer Figure 3-15. Block Diagram of PLL Frequency Synthesizer Internal bus PLL mode Select register (PLLMD) VCOH VCOL PLL PLL DMD DMD MD1 MD0 2 VCOH Mixer VCOL Input select block Programmable divider PLL data transfer register (PLLNS) PLL data register (PLLRL, PLLRH, PLLR0) 2 fN Phase comparator ( - DET) Charge pump EO0 EO1 PLL NS0 fr Note 1 Voltage control generator 6.3 MHz or 4.5 MHzNote 2 Reference frequency generator 4 Unlock F/F Note 1 Lowpass filter PLL PLL PLL PLL RF3 RF2 RF1 RF0 PLL reference mode register (PLLRF) PLL unlock F/F Judge register (PLLUL) Internal bus PLL UL0 Notes 1. These are external circuits. 2. When the IEBus controller of the PD178096 and 178098 is used, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz crystal resonator. Data Sheet U12885EJ3V0DS00 35 PD178076, 178078, 178096, 178098 3.9 Frequency Counter Figure 3-16. Block Diagram of Frequency Counter 2 Gate time control block FMIFC/P102 Input select block AMIFC/P101 Start/stop control block IF counter register (IFCR) block 2 IFC IFC IFC IFC MD1 MD0 CK1 CK0 IF counter mode select register (IFCMD) IF counter gate judge register IFC JG0 IFC IFC ST RES IF counter control register (IFCCR) Internal bus 36 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 4. INTERRUPT FUNCTION (1) PD178076 and 178078 The PD178076 and 178078 have the following three types and 22 sources of interrupts: * Non-maskable : 1Note * Maskable * Software Note : 21Note :1 Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and either of them can be selected. Table 4-1. Interrupt Sources (PD178076 and 178078) (1/2) Default Interrupt Type PriorityNote 1 Non-maskable Maskable - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTCSI0 INTCSI1 INTCSI3 INTTM50 End of transfer by serial interface 0 End of transfer by serial interface 1 End of transfer by serial interface 3 Generation of coincidence signal of 8-bit timer/event counter 50 Trigger Overflow of watchdog timer (when watchdog timer mode 1 is selected) Overflow of watchdog timer (when interval timer mode is selected) Pin input edge detection Internal/ External Internal Vector Basic Table Configuration Address TypeNote 2 0004H (A) (B) External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H (C) Internal 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H 0026H (B) INTTM51 Generation of coincidence signal of 8-bit timer/event counter 51 INTSER0 Reception error of serial interface UART0 INTSR0 INTST0 End of reception by serial interface UART0 End of transmission by serial interface UART0 INTBTM0 Generation of coincidence signal of basic timer Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 22 is the lowest. 2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1. Data Sheet U12885EJ3V0DS00 37 PD178076, 178078, 178096, 178098 Table 4-1. Interrupt Sources (PD178076 and 178078) (2/2) Default Interrupt Type PriorityNote 1 Maskable 18 Interrupt Source Name INTTM00 Trigger Generation of signal indicating coincidence between 16-bit timer counter (TM0) and capture/compare register (CR00) (when CR00 is used as compare register) Detection of input edge of TI00/P32 pin (when CR00 is used as capture register) 19 INTTM01 Generation of signal indicating coincidence between 16-bit timer counter (TM0) and capture/compare register (CR01) (when CR01 is used as compare register) Detection of input edge of TI01/P33 pin (when CR01 is used as capture register) 20 21 22 Software - - - INTAD BRK - - End of conversion by A/D converter Execution of BRK instruction Internal - Internal/ External Internal Vector Basic Table Configuration Address TypeNote 2 0028H (B) External Internal 002AH (D) (B) External - Note 3 Note 3 (D) - 0030H 003EH (B) (E) Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 22 is the lowest. 2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1. 3. There are no interrupt sources corresponding to vector addresses 002CH and 002EH. 38 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 (2) PD178096 and 178098 The PD178096 and 178098 have the following three types and 21 sources of interrupts: * Non-maskable : 1Note * Maskable * Software Note : 20Note :1 Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and either of them can be selected. Table 4-2. Interrupt Sources (PD178096 and 178098) (1/2) Default Interrupt Type PriorityNote 1 Non-maskable Maskable - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Interrupt Source Name INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTCSI0 INTCSI1 INTCSI3 INTTM50 INTTM51 - - - INTBTM0 End of transfer by serial interface 0 End of transfer by serial interface 1 End of transfer by serial interface 3 Generation of coincidence signal of 8-bit timer/event counter 50 Generation of coincidence signal of 8-bit timer/event counter 51 - - - Generation of coincidence signal of basic timer Trigger Overflow of watchdog timer (when watchdog timer mode 1 is selected) Overflow of watchdog timer (when interval timer mode is selected) Pin input edge detection Internal/ External Internal Vector Basic Table Configuration Address TypeNote 2 0004H (A) (B) External 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H (C) Internal 0016H 0018H 001AH 001CH 001EH (B) - Note 3 Note 3 Note 3 - Internal 0026H (B) Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 22 is the lowest. 2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1. 3. There are no interrupt sources corresponding to vector addresses 0020H, 0022H, and 0024H. Data Sheet U12885EJ3V0DS00 39 PD178076, 178078, 178096, 178098 Table 4-2. Interrupt Sources (PD178096 and 178098) (2/2) Default Interrupt Type PriorityNote 1 Maskable 18 Interrupt Source Name INTTM00 Trigger Generation of signal indicating coincidence between 16-bit timer counter (TM0) and capture/compare register (CR00) (when CR00 is used as compare register) Detection of input edge of TI00/P32 pin (when CR00 is used as capture register) 19 INTTM01 Generation of signal indicating coincidence between 16-bit timer counter (TM0) and capture/compare register (CR01) (when CR01 is used as compare register) Detection of input edge of TI01/P33 pin (when CR01 is used as capture register) 20 21 22 Software - INTIE1 INTIE2 INTAD BRK IEBus0 data access request IEBus0 communication error and start/end of communication End of conversion by A/D converter AD1 Execution of BRK instruction - Internal/ External Internal Vector Basic Table Configuration Address TypeNote 2 0028H (B) External Internal 002AH (D) (B) External Internal 002CH 002EH 0030H 003EH (D) (B) (B) (E) Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 22 is the lowest. 2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1. 40 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Figure 4-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Priority control circuit Vector table address generation circuit Standby release signal (B) Internal maskable interrupt Internal bus MK IE PR ISP Interrupt request IF Priority control circuit Vector table address generation circuit Standby release signal (C) External maskable interrupt (INTP0 through INTP7) Internal bus External interrupt rising/falling edge enable registers (EGP, EGN) MK IE PR ISP Interrupt request Edge detection circuit IF Priority control circuit Vector table address generation circuit Standby release signal Data Sheet U12885EJ3V0DS00 41 PD178076, 178078, 178096, 178098 Figure 4-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupts (INTTM00, INTTM01) Internal bus Prescaler mode register (PRM0) MK IE PR ISP Interrupt request Edge detection circuit IF Priority control circuit Vector table address generation circuit Standby release signal (E) Software interrupt Internal bus Interrupt request Priority control circuit Vector table address generation circuit Remark IF : Interrupt request flag IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 42 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 5. STANDBY FUNCTION There are the following two standby functions to reduce the system power consumption. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operating mode. * STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and current consumption can be considerably reduced. Figure 5-1. Standby Function System Clock Operation STOP Instruction Interrupt Request HALT Mode (Clock supply to CPU is stopped, oscillation continued) HALT Instruction Interrupt Request STOP Mode (System clock oscillation stopped) 6. RESET FUNCTION There are the following three reset methods. * External reset input by RESET pin * Internal reset by watchdog timer hang-up time detection * Internal reset by Power-On Clear (POC). Data Sheet U12885EJ3V0DS00 43 PD178076, 178078, 178096, 178098 7. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand First Operand A #byte A r [HL + byte] Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] [HL + C] $addr16 1 None ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV INC DEC B,C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ DBNZ INC DEC !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV MOV MOV PUSH POP ROR4 ROL4 MOV MOV MULU DIVUW Note Except r = A 44 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX #word ADDW SUBW CMPW rp MOVW MOVW Note INCW DECW PUSH POP AX rp Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW Note Only when rp = BC, DE or HL Data Sheet U12885EJ3V0DS00 45 PD178076, 178078, 178096, 178098 (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand First Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 (4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 46 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD VDDPORT AVDD VDDPLL Input voltage Output voltage Output breakdown voltage Analog input voltage High-level output current VAN IOH P10-P17 1 pin Total of P00-P01, P20-P27, P50-P57, and P70-P73 Total of P02-P07, P30-P37, P40-P47, P60-P67, P74-P77, and P120-P124 Total of P100-P102 Low-level output current IOL Note 2 1 pin Peak value r.m.s Total of P00-P01, P20-P27, P50-P57, Peak value and P70-P73 r.m.s -10 16 8 30 15 30 15 mA mA mA mA mA mA mA Analog input pin -0.3 to VDD + 0.3 -8 -15 -15 V mA mA mA VI VO VBDS Excluding P130 to P137 P130-P137 N-ch open drain Conditions Rating -0.3 to +6.0 -0.3 to VDD + 0.3Note 1 -0.3 to VDD + 0.3Note 1 -0.3 to VDD + 0.3Note 1 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 16 Unit V V V V V V V Total of P02-P07, P30-P37, P40-P47, Peak value P60-P67, P74-P77, P120-P124, and P130-P137 Total of P100-102 Peak value r.m.s Operating temperature Storage temperature TA Tstg r.m.s 20 10 -40 to +85 -55 to +125 mA mA C C Notes 1. Keep the voltage at VDDPORT, AVDD, and VDDPLL same as that at the VDD pin. 2. Calculate the r.m.s as follows: [r.m.s] = [Peak value] x Duty Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Be sure to use the product with these ratings never being exceeded. Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. Data Sheet U12885EJ3V0DS00 47 PD178076,178078,178096,178098 Recommended Supply Voltage Ranges (TA = -40 to +85C) Parameter Supply voltage Symbol VDD1 VDD2 Data retention voltage Output breakdown voltage VDDR VBDS Conditions When CPU and PLL are operating When CPU is operating and PLL is stopped When crystal oscillation stops P130-P137 (N-ch open drain) MIN. 4.5 3.5 2.3 TYP. 5.0 5.0 MAX. 5.5 5.5 5.5 15 Unit V V V V DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V) Parameter High-level input voltage Symbol VIH1 Test Conditions P10-P17, P21, P23, P30, P31, P36, P37, P40-P47, P50-P57, P60-P67, P71, P73, P75-P77, P100-P102, P120, P122-P124 P00-P07, P20, P22, P24-P27, P32-P35, P70, P72, P74, P121, RESET P10-P17, P21, P23, P30, P31, P36, P37, P40-P47, P50-P57, P60-P67, P71, P73, P75-P77, P100-P102, P120, P122-P124 P00-P07, P20, P22, P24-P27, P32-P35, P70, P72, P74, P121, RESET P00-P07, P20-P24, P30-P37, 4.5 V VDD 5.5 V, P40-P47, P50-P57, P60-P67, IOH = -1 mA P70-P77, P100-P102, 3.5 V VDD < 4.5 V, P120-P124 IOH = -100 A EO0, EO1 VDD = 4.5 to 5.5 V, IOH = -3 mA MIN. 0.7 VDD TYP. MAX. VDD Unit V VIH2 0.8 VDD VDD V Low-level input voltage VIL1 0 0.3 VDD V VIL2 0 0.2 VDD V High-level output voltage VOH1 VDD - 1.0 V VDD - 0.5 V VOH2 VDD - 1.0 V Low-level output voltage VOH1 P00-P07, P20-P27, P30-P37, 4.5 V VDD 5.5 V, P40-P47, P50-P57, P60-P67, IOL = 1 mA P70-P77, P100-P102, 3.5 V VDD < 4.5 V, P120-P124, P130-P137, IOL = 100 A EO0, EO1 VDD = 4.5 to 5.5 V, IOL = 3 mA VI = VDD 1.0 V 0.5 V VOL2 1.0 V High-level input leakage current ILIH P00-P07, P10-P17, P20-P24, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P100-P102, P120-P124, RESET 3 A Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. 48 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 DC Characteristics (TA = -40 to +85C, VDD = 3.5 to 5.5 V) Parameter Low-level input leakage current Symbol ILIL Conditions P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P100-P102, P120-P124, RESET P130-P137 P130-P137 P25-P27 (at N-ch open drain I/O) P25-P27 (at N-ch open drain I/O) EO0, EO1 EO0, EO1 When CPU is operating and PLL is stopped. Sine wave input to X1 pin VI = VDD VI = 0 V MIN. TYP. MAX. -3 Unit A Output off leakage current ILOH1 ILOL1 ILOH2 VO = 15 V VO = 0 V VO = VDD -3 3 -3 A A A A A A mA ILOL2 VO = 0 V 3 ILOH3 ILOL3 Supply currentNote IDD1 VO = VDD VO = 0 V fx = 4.5 MHz (PD178076, 178078) fx = 6.3 MHz (PD178076, 178078, 178096, 178098) fx = 4.5 MHz (PD178076, 178078) fx = 6.3 MHz (PD178076, 178078, 178096, 178098) 3.5 2.2 2.5 -3 3 15 IDD2 4.0 20 mA IDD3 IDD4 In HALT mode with PLL stopped. Sine wave input to X1 pin VI = VDD 0.2 0.8 mA 0.3 1.0 mA Data retention voltage VDDR1 VDDR2 When crystal resonator is oscillating When crystal oscillation is stopped Power-failure detection function Data memory retained When crystal oscillation is stopped TA = 25C, VDD = 5 V 5.5 V V VDDR3 Data retention current IDDR1 2.0 2.0 4.0 V A A IDDR2 2.0 20 Note Excluding AVDD current and VDDPLL current. Remarks 1. fX: System clock oscillation frequency 2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. Data Sheet U12885EJ3V0DS00 49 PD178076,178078,178096,178098 Reference Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V) Parameter Supply current Symbol IDD5 Conditions When CPU and PLL are operating. Sine wave input to VCOH pin At fIN = 160 MHz, VIN = 0.15 VP-P MIN. TYP. 5 MAX. Unit mA AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 3.5 to 5.5 V) Parameter Cycle time (minimum instruction execution time) TI00, TI01 input high-/low-level widths TI50, TI51 input frequency TI50, TI51 input high-/low-level widths Interrupt input high-/low-level widths RESET pin low-level width tTIH5, tTIL5 200 ns tTIH0, tTIL0 Symbol TCY At fX = 6.3 MHz At fX = 4.5 MHzNote 1 Conditions MIN. 0.32 0.44 TYP. MAX. 5.08 7.11 Unit s s 4/fsamNote 2 s fTI5 2 MHz tINTH, tINTL INTP0-INTP7 1 s tRSL 10 s Notes 1. When the IEBus controller of the PD178096 and 178098 is used, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz crystal resonator. 2. fsam = fX/2, fX/4, fX/64 selectable by bits 0 and 1 (PRM00 and PRM01) of the prescaler mode register 0 (PRM0). However, fsam = fX/8 when the valid edge of TI00 is selected as the count clock. 50 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 (2) Serial interface (TA = -40 to +85C, VDD = 3.5 to 5.5 V) (a) Serial interface 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output) Parameter SCK0 cycle time Symbol tKCY1 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 1600 SCK0 high-/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 100 100 150 SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSI1 tKSO1 C = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns ns 400 300 ns Note C is the load capacitance of SCK0 and SO0 output line. (ii) 3-wire serial I/O mode (SCK0 ... external clock input) Parameter Symbol tKCY2 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 1600 TYP. MAX. Unit ns ns ns ns ns ns 300 1000 ns ns SCK0 cycle time SCK0 high-/low-level width tKH2, tKL2 VDD = 4.5 to 5.5 V 400 800 100 400 SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 at rising or falling edge time tSIK2 tKSI2 tKSO2 tR2, tF2 C = 100 pF Note Note C is the load capacitance of SO0 output line. Data Sheet U12885EJ3V0DS00 51 PD178076,178078,178096,178098 (iii) SBI mode (SCK0 ... internal clock output) Parameter SCK0 cycle time Symbol tKCY3 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high-/low-level width tKH3, tKL3 SB0, SB1 setup time (to SCK0) tSIK3 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY3/2 - 50 tKCY3/2 - 150 100 300 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSI3 tKSO3 R = 1 k C = 100 pF Note VDD = 4.5 to 5.5 V tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line. (iv) SBI mode (SCK0 ... external clock input) Parameter SCK0 cycle time Symbol tKCY4 Test Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high-/low-level width tKH4, tKL4 SB0, SB1 setup time (to SCK0) tSIK4 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 300 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 at rising or falling edge time tKSB tSBK tSBH tSBL tR4, tF4 tKSI4 tKSO4 R = 1 k C = 100 pF Note VDD = 4.5 to 5.5 V tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 1000 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note R and C are the load resistance and load capacitance of SB0 and SB1 output line. 52 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 (v) 2-wire serial I/O mode (SCK0 ... internal clock output) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 Test Conditions R = 1 k C = 100 pF Note MIN. 1600 tKCY5/2 - 160 TYP. MAX. Unit ns ns ns ns ns ns ns VDD = 4.5 to 5.5 V tKCY5/2 - 50 tKCY5/2 - 100 SB0, SB1 setup time (to SCK0) tSIK5 VDD = 4.5 to 5.5 V 300 350 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSI5 tKSO5 600 0 300 ns Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0 ... external clock input) Parameter Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 R = 1 k C = 100 pF tR6, tF6 Note Test Conditions MIN. 1600 650 800 100 tKCY6/2 TYP. MAX. Unit ns ns ns ns ns SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 at rising or falling edge time VDD = 4.5 to 5.5 V 0 0 300 500 1000 ns ns ns Note R and C are the load resistance and load capacitance of SB0 and SB1 output line. Data Sheet U12885EJ3V0DS00 53 PD178076,178078,178096,178098 (vii) I 2C Bus mode (SCL ... internal clock output) Parameter SCL cycle time SCL high-level width SCL low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time (from SCL) SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width tKSB Symbol tKCY7 tKH7 tKL7 tSIK7 tKSI7 Test Conditions R = 1 k C = 100 pF Note MIN. 10 tKCY7 - 160 tKCY7 - 50 200 0 TYP. MAX. Unit s ns ns ns ns tKSO7 VDD = 4.5 to 5.5 V 0 0 200 300 500 ns ns ns tSBK tSBH 400 500 ns ns Note R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line. (viii) I2 C Bus mode (SCL ... external clock input) Parameter Symbol tKCY8 tKH8, tKL8 tSIK8 tKSI8 Test Conditions MIN. 1000 400 200 0 TYP. MAX. Unit ns ns ns ns SCL cycle time SCL high-/low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width SCL at rising or falling edge time tKSO8 R = 1 k C = 100 pF Note VDD = 4.5 to 5.5 V 0 0 200 300 500 ns ns ns tKSB tSBK tSBH tR8, tF8 400 500 1000 ns ns ns Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output line. 54 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 (b) Serial interface 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output) Parameter SCK1 cycle time SCK1 high/low-level width Symbol tKCY9 tKH9, tKL9 tSIK9 tKSI9 tKSO9 C = 100 pF Note Test Conditions MIN. 800 tKCY9/2 - 50 TYP. MAX. Unit ns ns SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) 100 400 300 ns ns ns Note C is the load capacitance of SCK1 and SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input) Parameter Symbol tKCY10 tKH10, tKL10 tSIK10 tKSI10 tKSO10 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns SCK1 cycle time SCK1 high/low-level width SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) 100 400 300 1000 ns ns ns ns SCK1 at rising or falling edge time tR10, tF10 Note C is the load capacitance of SO1 output line. Data Sheet U12885EJ3V0DS00 55 PD178076,178078,178096,178098 (iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock output) Parameter SCK1 cycle time SCK1 high/low-level width Symbol tKCY11 tKH11, tKL11 tSIK11 tKSI11 tKSO11 tSBD tSBW tBYS C = 100 pF Note tKCY11/2 - 100 tKCY11/2 - 30 100 Test Conditions MIN. 800 tKCY11/2 - 50 TYP. MAX. Unit ns ns SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive 100 400 300 tKCY11/2 + 100 tKCY11/2 + 30 ns ns ns ns ns ns tBYH 100 ns tSPS 200 ns Note C is the load capacitance of SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock input) Parameter Symbol tKCY12 tKH12, tKL12 tSIK12 tKSI12 tKSO12 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns SCK1 cycle time SCK1 high/low-level width SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1) 100 400 300 1000 ns ns ns ns SCK1 at rising or falling edge time tR12, tF12 Note C is the load capacitance of SO1 output line. 56 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 (c) Serial interface 3 (i) 3-wire serial I/O mode (SCK3 ... internal clock output) Parameter SCK3 cycle time SCK3 high/low-level width Symbol tKCY13 tKH13, tKL13 tSIK13 tKSI13 tKSO13 C = 100 pF Note Test Conditions MIN. 800 tKCY13/2 - 50 TYP. MAX. Unit ns ns SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time (from SCK3) 100 400 300 ns ns ns Note C is the load capacitance of SCK3 and SO3 output line. (ii) 3-wire serial I/O mode (SCK3 ... external clock input) Parameter Symbol tKCY14 tKH14, tKL14 tSIK14 tKSI14 tKSO14 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns SCK3 cycle time SCK3 high/low-level width SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time (from SCK3) 100 400 300 1000 ns ns ns ns SCK3 at rising or falling edge time tR14, tF14 Note C is the load capacitance of SO3 output line. (d) Serial interface UART0 (Dedicated baud rate generator output)Note Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 38400 Unit bps Note PD178076 and 178078 only. Data Sheet U12885EJ3V0DS00 57 PD178076,178078,178096,178098 AC Timing Test Point (Excluding X1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test Points TI Timing tTIL0 tTIH0 TI00, TI01 1/fTI5 tTIL5 tTIH5 TI50,TI51 Interrupt Input Timing tINTL tINTH INTP0 to INTP7 RESET Input Timing tRSL RESET 58 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tRn SCK0, SCK1, SCK3 tSIKm tKSIm tKHm tFn SI0, SI1, SI3 tKSOm Input Data SO0, SO1, SO3 Output Data Remark m = 1, 2, 9, 10, 13, 14 n = 2, 10, 14 SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4 SB0, SB1 tKSO3, 4 Data Sheet U12885EJ3V0DS00 59 PD178076,178078,178096,178098 SBI mode (command signal transfer): tKCY3, 4 tKL3, 4 tR4 tKH3, 4 tF4 SCK0 tSIK3, 4 tKSB tSBK tKSI3, 4 SB0, SB1 tKSO3, 4 2-wire serial I/O mode: tKCY5, 6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 SB0, SB1 tKSI5, 6 tKH5, 6 tF6 I 2C bus mode: tF8 SCL tKL7, 8 tKSI7, 8 tKH7, 8 tSIK7, 8 tKSO7, 8 tR8 tKCY7, 8 tKSB tSBK tKSB SDA0, SDA1 tSBH tSBK 60 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 3-wire serial I/O mode with automatic transmit/receive function: SO1 D2 D1 D0 D7 SI1 D2 tSIK11, 12 tKSO11, 12 D1 D0 tKSI11, 12 tKH11, 12 tF12 D7 SCK1 tR12 tKL11, 12 STB tKCY11, 12 tSBD tSBW 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCK1 7 8 9 Note 10 Note tBYS 10 + n Note tBYH tSPS 1 BUSY (Active high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. IEBus Controller CharacteristicsNote 1 (TA = -40 to +85C, VDD = 3.5 to 5.5 V) Parameter IEBus system clock frequency Symbol fs Fixed to mode 1 Conditions MIN. TYP. 6.3Note 2 MAX. Unit MHz Notes 1. PD178096 and 178098 only. 2. Although the system clock frequency is 6.0 MHz in the IEBus standard, in these products, normal operation is guaranteed at 6.3 MHz. Remark 6.0 MHz and 6.3 MHz cannot both be used as the IEBus system clock frequency. Data Sheet U12885EJ3V0DS00 61 PD178076,178078,178096,178098 A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = 3.5 to 5.5 V) Parameter Resolution Total conversion errorNotes 1, 2 Conversion time Analog input voltage tCONV VIAN 15.2 0 VDD = 4.5 to 5.5 V Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.0 1.4 45.7 VDD Unit bit %FSR %FSR s V Notes 1. Excluding quantization error (0.2%FSR) 2. This value is indicated as a ratio to the full-scall value. PLL Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN1 fIN2 fIN3 fIN4 Conditions VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P MIN. 0.5 10 60 40 TYP. MAX. 3.0 40 130 160 Unit MHz MHz MHz MHz Remark The above values are the result of NEC's evaluation of the device. If the device is likely to be affected by noise in your application, it is recommended to use the device at a voltage higher than the above values. IFC Characteristics (TA = -40 to +85C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN5 Conditions AMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P FMIFC pin, FMIF count mode, sine wave input, VIN = 0.15 VP-P FMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P MIN. 0.4 TYP. MAX. 0.5 Unit MHz fIN6 10 11 MHz fIN7 0.4 0.5 MHz Remark The above values are the result of NEC's evaluation of the device. If the device is likely to be affected by noise in your application, it is recommended to use the device at a voltage higher than the above values. 62 Data Sheet U12885EJ3V0DS00 PD178076,178078,178096,178098 9. PACKAGE DRAWING 100-PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end S CD Q R 100 1 31 30 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. P100GF-65-3BA1-4 Data Sheet U12885EJ3V0DS00 63 PD178076,178078,178096,178098 10. RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Table 10-1. Soldering Conditions for Surface-Mount Type PD178076GF-XXX-3BA: 100-pin plastic QFP (14 x 20) PD178078GF-XXX-3BA: 100-pin plastic QFP (14 x 20) PD178096GF-XXX-3BA: 100-pin plastic QFP (14 x 20) PD178098GF-XXX-3BA: 100-pin plastic QFP (14 x 20) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 sec max. (210C min.), Number of times: 3 max. Package peak temperature: 215C, Time: 40 sec max. (200C min.), Number of times: 3 max. Solder bath temperature: 260C max., Time: 10 sec max., Number of times: 1, Preheating temperature: 120C max., (Package surface temperature) Pin temperature: 300C max., Time: 3 sec max (per device side) Recommended Conditions Symbol IR35-00-3 VPS VP15-00-3 Wave soldering WS60-00-1 Partial heating - Caution Do not use two or more soldering methods in combination (except partial heating). 64 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD178078 and 178098 subseries. Language processor software RA78K/0Notes 1, 2, 3 CC78K/0Notes 1, 2, 3 DF178098Notes 1, 2, 3 CC78K0-LNotes 1, 2, 3 Assembler package common to 78K/0 series C compiler package common to 78K/0 series Device file for PD178078 subseries and PD178098 subseries C compiler library source file common to 78K/0 series Flash memory writing tools Fashpro III (Part number: FL-PR3Note 4, PG-FL3) FA-100GF-3BANote 4 Dedicated flash programmer Flash programmer adapter Debugging tools * When in-circuit emulator IE-78K0-NS is used IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PA IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Power supply unit for IE-78K0-NS Performance board for enhancing and expanding the IE-78K0-NS function Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine (C bus supported) PC card and interface cable necessary when a notebook-type PC is used as host machine (PCMCIA socket supported) Interface adapter necessary when a IBM PC/ATTM compatible machine is used as host machine (ISA bus supported) Interface adapter necessary when a PC with a PCI bus is used as host machine Emulation board to emulate PD178078 and 178098 subseries Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type) System simulator common to 78K/0 series Integrated debugger common to 78K/0 series Device file for PD178078 subseries and PD178098 subseries IE-70000-CD-IF-A IE-70000-PC-IF-C IE-70000-PCI-IF IE-178098-NS-EM1 NP-100GFNote 4 EV-9200GF-100 SM78K0Notes 1, 2 ID78K0-NSNotes 1, 2 DF178098Notes 1, 2, 3 Notes 1. PC-9800 series (Japanese WindowsTM) based 2. IBM PC/AT compatible machine (Japanese/English windows) based 3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM (NEWS-OSTM) based 4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813). Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178098. Data Sheet U12885EJ3V0DS00 65 PD178076, 178078, 178096, 178098 * When in-circuit emulator IE-78001-R-A is used IE-78001-R-A IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine (C bus supported) Interface adapter necessary when IBM PC/AT compatible machine is used as host machine (ISA bus supported) Interface adapter necessary when a PC with a PCI bus is used as host machine Interface adapter and cable necessary when EWS is used as host machine Emulation board to emulate PD178078 and 178098 subseries Emulation probe conversion board necessary when using IE-178098-NS-EM1 on IE-78001-R-A Emulation probe for 100-pin plastic QFP (GF-3BA type) Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type) System simulator common to 78K/0 series Integrated debugger common to 78K/0 series Device file for PD178078 subseries and PD178098 subseries IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-178098-NS-EM1 IE-78K0-R-EX1 EP-78064GF-R EV-9200GF-100 SM78K0Notes 1, 2 ID78K0Notes 1, 2 DF178098Notes 1, 2, 3 Real-time OS RX78K/0Notes 1, 2, 3 MX78K0Notes 1, 2, 3 Real-time OS for 78K/0 series OS for 78K/0 series Notes 1. PC-9800 series (Japanese Windows) based 2. IBM PC/AT compatible machine (Japanese/English windows) based 3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEWS-OS) based Remark Use the SM78K0 in combination with the DF178098. 66 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Documents Title Document No. Japanese English This document U12920E U12790E U12326E U12704E PD178076, 178078, 178096, 178098 Data Sheet PD178F098 Data Sheet PD178078, 178098 Subseries User's Manual 78K/0 Series User's Manual - Instruction 78K/0 Series Application Note Basics (I) U12885J U12920J U12790J U12326J U12704J Development Tool Documents (User's Manual) Title RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K0 C Compiler Operation Language IE-78001-R-A IE-78K0-NS IE-178098-NS-EM1 EP-78064 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference Reference Guide Reference Operation U11517J U11518J U14142J U13731J U14013J EEU-934 U10181J U10092J U11517E U11518E To be prepared U13731E U14013E EEU-1469 U10181E U10092E U11802J U11801J U11789J Document No. Japanese English U11802E U11801E U11789E ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based ID78K0-NS Integrated Debugger Windows Based U11151J U11539J U11649J U12900J U14379J -- U11539E U11649E U12900E To be prepared Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. Data Sheet U12885EJ3V0DS00 67 PD178076, 178078, 178096, 178098 Related Documents for Embedded Software (User's Manual) Document No. Title Japanese 78K/0 Series Real-time OS Fundamental Installation 78K/0 Series OS MX78K0 Fundamental U11537J U11536J U12257J English U11537E U11536E U12257E Other Documents Document No. Title Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Guides on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality/Reliability Handbook Microcomputer Product Series Guide X13769X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E -- -- English Caution The contents of the above documents are subject to change without notice. Ensure that the latest versions are used in design work, etc. 68 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 [MEMO] Data Sheet U12885EJ3V0DS00 69 PD178076, 178078, 178096, 178098 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I 2C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 70 Data Sheet U12885EJ3V0DS00 PD178076, 178078, 178096, 178098 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U12885EJ3V0DS00 71 PD178076, 178078, 178096, 178098 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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